A stored-program computer successively executes programs stored in its main storage. The programs and data including variables used for executing the programs are electrically stored with, for example, electric charges.
When data is electrically stored, its values may be corrupted or altered under the influence of electrical noise, such as cosmic rays, static electricity, and other disturbances. Various methods are known to improve the error resilience of such data.
Techniques for detecting and correcting errors known in the art may use error detecting codes called parity bits, which are added to data when the data is stored. When the data is read, the read data and the corresponding parity bits are compared for detecting and correcting errors. Memory having this function may be referred to as error-correcting code (ECC) memory.
Japanese Unexamined Patent Application Publication No. 2009-146168 (Patent Literature 1) describes a technique for providing a component-mounting board for a programmable logic controller (PLC) that can support the specifications of an IO memory with a backup function and an IO memory with an ECC function at low cost.
However, the IO memory with the ECC function described for example in Patent Literature 1 includes a circuit configuration for implementing the ECC function and an additional capacity for storing parity bits, and is thus more costly than a memory without the ECC function. The memory without the ECC may thus have the function of self-diagnosis to prevent data corruption and misreading.
The memory self-diagnosis function is implemented as software in a program executed by a processor or in a circuit that reads data from the memory. This function adds an error-detecting code, such as a cyclic redundancy check (CRC), to data when the data is written, and diagnoses the data based on the error-detecting code when the data is read.